CISC 3320 Test 1 Review Sheet
1. CPU protection, memory protection, I/O protection.
2. Interrupts: Know what an interrupt is and know about interrupt processing, especially as implemented on the PC, including IRQ, interrupt vector, how the OS accomplishes transfer to and from the interrupt handler, what the interrupt handler does. Also: interrupt priorities, how and why interrupts may be disabled/enabled, what happens with multiple interrupts.
3. Processes and Threads: Know what a process is. Process control block. Process states, and how and when a process moves from one state to another. I/O bound vs CPU bound jobs. Long term scheduling. Threads: what a thread js and how it is different from a heavyweight process. Kernel level vs. user-level threads, advantages and disadvantages.
4. CPU Scheduling (short‑term scheduling): Scheduling criteria (CPU utilization, throughput, turnaround time, waiting time, dilation, response time). Be able to calculate turnaround time, waiting time, and dilation for a sequence of jobs. CPU burst‑I/O burst. Scheduling algorithms: FCFS, SJN (SJF), Round Robin, Shortest remaining time next, priority queues, multi-level queues, multi-level feedback queues. Be able to draw a Gantt diagram for a series of jobs. Be able to explain the difference between preemptive and non‑preemptive scheduling algorithms, and–given a scenario of jobs–explain which would run next. Time quantum and how to choose. Problems with various scheduling algorithms. When each algorithm is best.
5. Memory Management: swapping, "uniprogramming", fence register, MFP, MVP, simple paging, segmentation. Contiguous vs non-contiguous allocation. Implementation of each system: what is necessary to keep track of each job (tables, etc.), memory protection.
MFP: how jobs are assigned to partitions.
MVP: implementation of free space tables for First Fit, Best Fit, Worst Fit algorithms under MVP. How jobs are assigned to partitions. What happens to Free Space table when a job finishes. Fragmentation (external and internal, how much, where). Coälescing holes.
Paging: Page Map Table, PMTAR (PTBR), dynamic address translation. Access time. TLB. Associative memory. Hit ratio. Effective access time. Shared pages, reentrant code.
Segmentation: implementation with tables and with segment registers (PC). Protection. Problems with segmentation (space allocation, fragmentation). Paged segmentation as a solution: implementation.