Formal Verification with Series Parallel Posets

Abstract:
Formal Verification of hardware continues to grow in importance, as more and
more companies integrate verification into their product design and
development process. In this talk, we discuss a method of formal
verification based on the notion of series-parallel posets. We consider the
use of this method in verifying properties of simple non-iterated as well as
complex iterated systems, and illustrate the issues by demonstrating some
aspects of the verification of a pipelined microprocessor.