Pipelining

Pipelining divides the fetch–decode–execute cycle into separate stages, which may include:

1. Instruction fetch: The CPU fetches the instruction from memory.
2. Instruction decode: The instruction is decoded to understand what actions to perform.
3. Find operand addresses: calculate the address in main memory where each operand is stored.
4. Fetch Operands: The CPU fetches the instruction from main memory.
5. Execute Instruction: The CPU performs the operation specified by the instruction.
6. Write Back: The result of the operation is written back to the register or memory.

In a sequential fetch–decode–execute cycle, each instruction must complete all stages before the next instruction can start. This means that only one instruction is being processed at a time, which slows down overall performance.
If the CPU uses pipelining, however, each of these stages operates independently, allowing the CPU to process different parts of multiple instructions at the same time, thereby boosting the overall performance.