Cache Schemes: Direct-Mapped Cache

Now, if the CPU needs to check whether the variable with RAM address: $1011011001$ is currently located in cache or not, it will divide the bits of this address according to the format above.

    RAM Address
 Tag   Block  Offset
+----+-------+-----+
| 10 | 11011 | 001 |
+----+-------+-----+

Then, the CPU will check if the tag number $10$ is the same as the tag of the cache block $11011$:

• If yes, the CPU will access the variable at depth $001$ inside cache.
• If not, the CPU will need to access the variable inside RAM at address $1011011001$. Afterwards, it will copy the entire corresponding RAM block of data (block number $1011011$) into cache block number $11011$: this is one of the $2^7 = 128$ RAM blocks, and it is of the size of $8$ bytes (just like the size of any cache block.)