Cache Schemes: Fully Associative Cache

Because each RAM block can be copied anywhere in cache, we don't need to keep track of cache block numbers as part of a given RAM address, so the format of a RAM address will consist of a tag field and an offset (depth) field:

             RAM Address
+---------------------+------------+
|        Tag          |   Offset   |
+---------------------+------------+

If the CPU, for example, wants to check if the variable with the RAM address $1011011001$ is currently located in cache or not, it will check if any of the cache blocks has the tag of $1011011$. If yes, the CPU will get the variable at depth $001$ in that cache block. If not, the CPU will have to get the variable from RAM at address $1011011001$.

         Tag              Offset
+---------------------+------------+
|      1011011        |     001    |
+---------------------+------------+