Cache Schemes: Set-Associative Cache

Because each RAM block can be present in one of the blocks that belong to the set, the format of a RAM address will consist of a tag, set, and offset (depth) fields:

             RAM Address
+---------+-----------+------------+
|   Tag   |    Set    |   Offset   |
+---------+-----------+------------+

If cache is divided into $8$ sets, and if the CPU, for example, wants to check if the variable with the RAM address $1011011001$ is currently located in cache or not, it will check if any of the cache blocks in set $011$ has the tag of $1011$. If yes, the CPU will get the variable at depth $001$ in that cache block. If not, the CPU will have to get the variable from RAM at address $1011011001$.

    Tag        Set        Offset    
+---------+-----------+------------+
|  1011   |    011    |     001    |
+---------+-----------+------------+