RISC vs. CISC Architectures

RISC code typically uses simple $1$-cycle instructions, each performing a single operation such as load, store, or add.

For example, adding two numbers stored in memory in a RISC system might require the following $4$ instructions:

LOD R1, X
LOD R2, Y
ADD R3, R1
ADD R3, R2

in which we load the variables at the memory addresses X and Y into the CPU registers R1 and R2, and then add these values and store them in register R3.

Note that it takes the CPU one clock cycle to process each of these instructions.