One
common requirement in digital circuits
is counting, both forward and backward.
Digital clocks and watches are everywhere,
timers are found in a range of appliances
from microwave ovens to VCRs, and counters
for other reasons are found in everything
from automobiles to test equipment. Although
we will see many variations on the basic
counter, they are all fundamentally very
similar. The demonstration below shows
the most basic kind of binary counting
circuit.
-
A BASIC
DIGITAL 4-BIT COUNTER -
In
the 4-bit counter above, we are using
edge-triggered master-slave flip-flops
similar to those in the Sequential portion
of these pages. The output of each flip-flop
changes state on the falling edge (1-to-0
transistion) of the T input.
The
count held by this counter is read in
the reverse order from the order in which
the flip-flops are triggered. Thus, output
D is the high order of the count, while
output A is the low order. The binary
count held by the counter is then DCBA,
and runs from 0000 (decimal 0) to 1111
(decimal 15). The next clock pulse will
cause the counter to try to increment
to 10000 (decimal 16). However, that 1
bit is not held by any flip-flop and is
therefore lost. As a result, the counter
actually reverts to 0000, and the count
begins again.
Note,
that in this and in following demonstrations
instead of changing the state of the input
clock with each click, you will send one
complete clock pulse to the counter when
you click the input button. The button
image will reflect the state of the clock
pulse, and the counter image will be updated
at the end of the pulse.
The
problem with the above example of a Binary
Counter is that we do not want all flip-flops
to change state with every clock pulse.
Therefore, we'll need to add some controlling
gates to determine when each flip-flop
is allowed to change state, and when it
is not. This requirement denies us the
use of T flip-flops, but does require
that we still use edge-triggered circuits.
We can use either RS or JK flip-flops
for this; we'll use JK flip-flops for
the below demonstration.
Looking
first at output A, we note that it must
change state with every input clock pulse.
Therefore, we could use a T flip-flop
here if we wanted to. We won't do so,
just to make all of our flip-flops the
same. But even with JK flip-flops, all
we need to do here is to connect both
the J and K inputs of this flip-flop to
logic 1 in order to get the correct activity.
States
Count
D
C
B
A
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
Flip-flop
B is a bit more complicated. This output
must change state only on every other
input clock pulse. Looking at the truth
table again, output B must be ready to
change states whenever output A is a logic
1, but not when A is a logic 0. If we
recall the behavior of the JK flip-flop,
we can see that if we connect output A
to the J and K inputs of flip-flop B,
we will see output B behaving correctly.
Continuing
this line of reasoning, output C may change
state only when both A and B are logic
1. We can't use only output B as the control
for flip-flop C; that will allow C to
change state when the counter is in state
2, causing it to switch directly from
a count of 2 to a count of 7, and again
from a count of 10 to a count of 15 —
not a good way to count. Therefore we
will need a two-input AND gate at the
inputs to flip-flop C. Flip-flip D requires
a three-input AND gate for its control,
as outputs A, B, and C must all be at
logic 1 before D can be allowed to change
state.
When
we started our look into counters, we
noted a lot of applications involving
numeric displays: clocks, ovens, microwave
ovens, VCRs, etc. These applications require
a decimal count in most cases, and a count
from 0 to 5 for some digits in a clock
display. Can we use a method of gating,
such as we used above in the synchronous
binary counter, to shorten the counting
sequence to the appropriate extent?
In
some cases, we want a counter that provides
individual digit outputs rather than a
binary or BCD output. Of course, we can
do this by adding a decoder circuit to
the binary counter. However, in many cases
it is much simpler to use a different
counter structure, that will permit much
simpler decoding of individual digit outputs.
For
example, consider the counting sequence
below. It actually resembles the behavior
of a shift register more than a counter,
but that need not be a problem. Indeed,
we can easily use a shift register to
implement such a counter. In addition,
we can notice that each legal count may
be defined by the location of the last
flip-flop to change states, and which
way it changed state. This can be accomplished
with a simple two-input AND or NOR gate
monitoring the output states of two adjacent
flip-flops. In this way, we can use ten
simple 2-input gates to provide ten decoded
outputs for digits 0-9. This is known
as the Johnson counting sequence, and
counters that implement this approach
are called Johnson Counters.
States
Count
A
B
C
D
E
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
2
1
1
1
0
0
3
1
1
1
1
0
4
1
1
1
1
1
5
0
1
1
1
1
6
0
0
1
1
1
7
0
0
0
1
1
8
0
0
0
0
1
9
We
could also make an octal counter by using
four flip-flops in this configuration.
In fact, this is done commercially: the
CMOS ICs 4017 and 4022 are counters that
implement this technique easily and cheaply.
There
is one caveat that must be considered
here: The 5-stage circuit uses five flip-flops,
and therefore has 32 possible binary states,
yet we only use ten states. The 4-stage
counter uses only eight of 16 possible
states. We must include circuitry that
will filter out the illegal states and
force this circuit to go towards the correct
counting sequence, even if it finds itself
in an illegal mode when first powered
up. This is not difficult, and the demonstration
circuit below includes the necessary gating
structure.
The
circuit below is logically equivalent
to the CMOS 4017 decimal counter, although
slightly simplified from the commercial
unit.
